Method of Forming a Semiconductor Device Having a Dummy Feature

ABSTRACT

A method for forming a semiconductor device includes identifying an area that comprises an active device region, wherein the area has a perimeter at a first location and at least a portion of the edge of the active device region is coincident with at least a portion of the perimeter, expanding the perimeter to a first distance away from the first location, wherein the first distance defines a first point of a dummy feature, determining a second point of the dummy feature, adding the dummy feature to a layout using the first point and the second point, and using the layout to form a layer in a semiconductor device.

FIELD OF THE INVENTION

This invention relates generally to semiconductor devices, and morespecifically, to forming semiconductor devices with dummy etch features.

BACKGROUND OF THE INVENTION

To increase device speed, the lengths of gate electrodes are decreasing.At the small dimensions that are currently used, it is important thatthe gate electrode has straight sidewalls. If the top of the gateelectrode is etched more than the bottom, then the small area of the topof the gate electrode makes it difficult to salicide the top of the gateelectrode. If, instead, the bottom of the gate electrode is narrowerthan the top, a shadow effect occurs making it difficult to implantsource and drain regions adjacent the gate electrode. The profile of thesidewalls is predominantly determined by etching.

Etching also can create a nonuniformity of the critical dimension offeatures, such as gate electrodes, across the wafer. For example, thedimension of a feature in one area of the wafer may be a larger than thedimension of another feature in a different area of the wafer eventhough the two features are intended to have the same dimension. Thisnon-uniformity of dimension can be caused by non-uniformity in thelocation of neighboring features. This nonuniformity in neighbor featurelocation is typically most important within 1 to 10 microns of thefeature with critical dimension. In addition to affecting the criticaldimension of the feature the nonuniformity of neighboring featurelocation also negatively impacts the final gate profile of the feature.

One proposal for improving the dimension and gate profile uniformity isto have dummy features placed adjacent isolated critical feature edges.This may be performed manually by placing dummy features, havingpredetermined shapes and dimensions near active circuit features.However, this is time consuming and subject to error. Hence, a fast,robust, and efficient method for placing dummy features is needed.

SUMMARY OF THE INVENTION

The present invention provides a method for forming a semiconductordevice having a dummy feature as described in the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and is notlimited by the accompanying figures, in which like references indicatesimilar elements.

FIG. 1 illustrates a top down view of a portion of an example of alayout of a semiconductor device;

FIG. 2 illustrates the layout of FIG. 1 illustrating a perimeter of anarea;

FIG. 3 illustrates the layout of FIG. 1 after moving a perimeter a firstdistance in accordance with an embodiment of the present invention;

FIG. 4 illustrates the layout of FIG. 1 after moving a perimeter asecond distance in accordance with an embodiment of the presentinvention;

FIG. 5 illustrates the layout of FIG. 1 after adding a first dummyfeature and a second dummy feature in accordance with an embodiment ofthe present invention;

FIG. 6 illustrates the layout of FIG. 1 after enlarging the second dummyfeatures in accordance with an embodiment of the present invention;

FIG. 7 illustrates the layout of FIG. 6 after a third dummy feature isadded underneath the second dummy features in accordance with anembodiment of the present invention;

FIG. 8 illustrates a top down view of another portion of a layout of asemiconductor device in accordance with an embodiment of the presentinvention;

FIG. 9 illustrates a top down view of FIG. 8 after enlarging a sixthactive feature or forming a third dummy feature; and

FIG. 10 illustrates a top down view of FIG. 5 after forming a thirddummy feature.

Skilled artisans appreciate that elements in the figures are illustratedfor simplicity and clarity and have not necessarily been drawn to scale.For example, the dimensions of some of the elements in the figures maybe exaggerated relative to other elements to help improve theunderstanding of the embodiments of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Three terms are defined below to aid in the understanding thespecification.

1. Active circuit features are features that correspond to the designedcircuitry for a semiconductor device. The active features includeportions of transistors, capacitors, resistors, or the like. Activefeatures include power supply features, which are designed to operate ata substantially constant potential, and signal features, which aredesigned to operate at one potential under one set of electronicconditions and a different potential at another set of electronicconditions. Active circuit features are not features that help controlthe processing of a substrate, such as alignment marks, structures formeasuring dimensions of features (“CD bars”), electrical teststructures, and the like. Active feature are also not features having aprimary (most important) function of protecting a semiconductor devicefrom post-fabrication environmental conditions, such as an edge ringseal around a die.

2. Dummy features include features printed onto a semiconductor devicesubstrate, where the features are not any of the other types of featuresdescribed above. Different types of dummy features are used insemiconductor devices for various reasons. Dummy bit lines are used inmemory arrays along the outermost edges to allow all the active bitlines in the array to be uniformly patterned. Unlike dummy bit lines,dummy etch features are dummy features added at a feature level of amask of a semiconductor device to improve etching characteristics at thecurrent or a subsequently formed level. A dummy etch feature is notrequired for the proper operation of a device.

3. Active device area is the portion of the die that is used inconjunction with the active circuit features to form a device. Theactive device area does not include the peripheral area of a die (i.e.,the portion of a die that lies between the integrated circuit area andthe scribe lines) or any insulated regions on the die.

FIG. 1 illustrates a portion of a layout 10 used to form a semiconductordevice. A skilled artisan recognizes that there may be layers andfeatures underneath the layout 10, but since the present invention is,for the most part, composed of layers, electronic components, andcircuits known to those skilled in the art, details will not beexplained in any greater extent than that considered necessary asillustrated below, for the understanding and appreciation of theunderlying concepts of the present invention and in order not toobfuscate or distract from the teachings of the present invention.

The layout 10 includes first active circuit features 20, second activecircuit features 22, and third active circuit features 24. In oneembodiment, the first, second, and third active circuit features 20, 22,and 24 are all portions of gate electrodes and may be any suitable gateelectrode material, such as polysilicon. Portions 17 of the first activecircuit features 20 and the second active circuit features 22 are withinthe first active device area 16, and portions 19 of the first activecircuit feature 20 are not within the active device area 16. Portions 9of the second active circuit features 22 are within a cut-out region 7of the first active device area 16. The cut-out region 7 is formed sothat the end of the second active circuit features 22 does not end onthe first active device area 16. In one embodiment, the cut-out region 7is an insulating layer. Portions (not marked) of the third activecircuit feature 24 are within the second active device area 12. Thefirst active device area 16 has a perimeter 18 and the second activedevice area 12 has a perimeter 14. In one embodiment, the first activedevice area 16 and the second active device area 12 are a portions ofthe semiconductor substrate that are doped with a p-type or n-typedopant; the first active device area 16 and the second active devicearea 12, may be doped the same conductivity or different conductivities.The underlying semiconductor substrate, which may be the exposed region25, can be any semiconductor material or combinations of materials, suchas gallium arsenide, silicon germanium, silicon-on-insulator (SOI)(e.g., fully depleted SOI (FDSOI)), silicon, monocrystalline silicon,the like, and combinations of the above. The p-type dopant can be anysuitable dopant, such as boron if the semiconductor substrate issilicon, and the n-type dopant can be any suitable dopant, such asphosphorus if the semiconductor substrate is silicon. Alternatively, theexposed region 25 may be an insulating layer or a combination of aninsulating layer and a semiconductor layer.

At least one dummy feature is added to the layer 10. In the embodimentillustrated in the figures, two dummy features are added. In oneembodiment, the location and shapes of the dummy features are determinedby expanding the perimeter of an area. First, the area is identified bychoosing an area that includes an active device region and may includeportions of active circuit features that are not within or overlie theactive device region. Next, the perimeter of the active device region isdefined. In one embodiment, the area includes the first active deviceregion 16 and any features or portions 17, which are within the activedevice region 16, so that the perimeter of the area is the perimeter 18of the active device region 16. In another embodiment, the area includesthe first active region 16, features within the active device region 16,and features and portions of the first circuit devices 20 that are notwithin the active device region 16, such as portions 19 of the firstcircuit devices 20. The portions 19 of the first circuit devices 20 maybe part of the area being defined to avoid placing a dummy feature tooclose to a circuit device. In this embodiment, the perimeter of the areais marked by the dotted line 11 in FIG. 2. In this embodiment, theperimeter of the area includes the perimeter 18 (FIG. 1) of the activedevice region 16 except where the first circuit devices 20 extend pastthe active device region. In the locations where the perimeter 18(FIG. 1) is not part of the perimeter of the area, the perimeter of thearea in these locations is the perimeter of the portions 19. Therefore,at least a portion of the perimeter is coincident with a portion of theperimeter 18 (FIG. 1) of active device region 16. As described above, inone embodiment, the perimeter of the area may also be coincident with aportion of the perimeter of the portions 19.

Once the perimeter is defined, it is moved a first distance away fromits original location. In other words, the perimeter is moved so thatthe area defined by the perimeter is enlarged. As shown in theembodiment in FIG. 3, the perimeter 11 is moved a first distance to theline marked 13. In one embodiment, this is done using software, such asdesign rule checking (DRC) software. One type of DRC software isCalibre® from Mentor Graphics® headquartered in Wilsonville, Oreg. Inanother embodiment, the perimeter is moved to a first distance manually.As will better be understood after further explanation, if a dummyfeature is to be placed, a point on the perimeter at a first distancewill be at least a first point of the dummy feature.

After expanding the perimeter to the first distance, a second point ofthe dummy feature is defined. In one embodiment, this is performed bymoving the perimeter to a second distance, where the second distance isfurther away than the first distance. As shown in the embodiment in FIG.4, the perimeter 11 is moved a first distance to the line marked 15. Theperimeter can be moved by any method used to move the perimeter to thefirst distance, although the same method may not be used for moving theperimeter both a first distance and a second distance. In anotherembodiment, the second point is determined by expanding the firstperimeter, expanding perimeters of adjacent areas (not shown), the like,or combinations of the above.

As shown in FIG. 5, after at least the second point of the dummy featureis defined, at least one dummy feature is added to the layout. In oneembodiment, a plurality of dummy features is added. However, placeswhere the addition of a dummy feature will be too close to activecircuit features or active regions, dummy features (or portions thereof)are not added. For example, a first dummy feature 26 and a second dummyfeature 28 are added to the layout, but no dummy features are formedover the second active device area 12 and third active circuit feature24. The layout 10 now includes the first dummy feature 28 and the seconddummy feature 26. In a preferred embodiment, the first and second dummyfeatures 28 and 26 are etch dummy features because they are used toimprove the etch profile of surrounding active circuit features. Inorder to assist with etch processing, the dummy features are formed onthe reticle and on the semiconductor device. In one embodiment, thefirst and second dummy features 28 and 26 may be the same materials aseach other or any of the first, second, and third active circuitfeatures 20, 22, and 24 and formed at the same time using the sameprocessing as the first, second, and third active circuit features 20,22, and 24.

Subsequent processes may include an optical proximity correction (OPC)process, as performed in the prior art, to assist with the printing ofthe first, second, and third active circuit features 20, 22, and 24.However, in one embodiment, the first and second dummy features 28 and26 are not used in the OPC process. This can be achieved by forming alayer in the DRC software that includes only the dummy features and bynot including this layer in those that are used in the OPC process.

The first and second dummy features 26 and 28 are placed using at leastthe first point and second point previously determined. In theembodiment illustrated in the figures, the edges of the dummy features26 and 28 that are closest to the original (unmoved) location of theperimeter 11 were determined and are contiguous with the location of theperimeter when moved a the first distance 13, and the edges that arefarthest from the perimeter 11 were determined and are contiguous withthe location of the perimeter when moved to the second distance 15.Thus, the difference between the first and second distances may be thewidth of a dummy feature because each of the first and second points iscoincident with an edge of the dummy feature. In one embodiment, thedifference between the first and second distances is ½ the width of adummy feature because the first point defined a point on the edge of thedummy feature and the second point defined a point in the center of thedummy feature. Because the perimeter of the active circuit regionincludes, in the embodiment shown in FIG. 1, the active region 16 andthe portions 19, the first and second dummy features 26 and 28 each haveedges that corresponds to the shape of the perimeter adjacent the dummyfeatures 24 and 26. The first dummy feature 26 protects the ends of thesecond active circuit features 22 and the second dummy feature 28protects the edges of the first active circuit features 24 because boththe line ends and edges are prone to deformation during subsequentprocessing, such as etching.

After forming at least one dummy feature, modifications to the layout,which now includes a dummy feature or a plurality of dummy features, maybe made to minimize the electrical and processing, such as etch, effectsof forming the dummy features. In other words, after adding the dummyfeatures, the layout may be optimized. Any of the approaches discussedbelow can be used alone or in combination with other approachesdiscussed.

One approach to optimize the layout that includes dummy features is tomodify the dummy features. In one embodiment, a dummy feature may bemodified to adjust for the subsequent etch processing. In oneembodiment, the dummy feature may be too far away from at least aportion of an active circuit feature that the dummy feature may notachieve the critical dimension of the active circuit feature (or portionthereof). In other words, the dummy feature may not prevent the activecircuit feature (or potion thereof) from being modified from the desireddimensions during etch. This may occur because the dummy feature is toofar from the active circuit feature because the etch profile of afeature is determined on a small size scale (less than approximately 10microns, which in one embodiment is approximately 1-10 microns, or 1-5microns). For example, without adjusting the dummy feature the activecircuit feature may be etched so that it is too narrow. Thus, the dummyfeature may need to be moved closer to the active circuit feature orincrease in size so that the active circuit feature (or portion thereof)will be the desired dimension after etching. For example, the dummyfeature may be increased in area. In the embodiment shown in FIG. 6, atleast one edge of the first dummy feature 26 is expanded so that theexpanded second dummy feature 30 has a larger area than the (original)first dummy feature 26. Thus, the critical dimension of the activecircuit feature determined after etch may be optimized by moving atleast an edge of a dummy feature. In one embodiment, this can beperformed by using etch simulation to optimize the dimension or profileof the active circuit feature.

In one embodiment, the dummy feature is modified so that it is undoped.Typically, dummy features are doped when the surrounding areas of thedummy features are doped. For simplicity in processing the dummyfeatures are also doped. It is desirable to prevent the dummy featuresfrom being doped, which can be performed by shielding them duringimplantation with a mask (such as photoresist). By having the dummyfeatures undoped resistance is increased and capacitance is decreased.For example, a switching signal adjacent a sensing line may createcross-talk. By forming a dummy feature, the switching line may beaffected so that it is too close to the sensing line, especially if thedummy feature is electrically coupled to the switching line which assubsequently explained and shown in FIG. 9 may occur. The closeness ofthe dummy feature to the switching line creates cross-talk. But if thedummy feature is undoped then conductivity and capacitance, and hencecross-talk, is decreased.

Another way to optimize the layout that includes dummy features is tomodify parts of the layout other than the dummy features themselves. Inone embodiment, layers underlying the dummy features are modified toaffect the capacitance and electrical characteristics of the dummyfeatures. For example, as shown in FIG. 7, a portion of the areaunderneath the dummy feature, which may be portion of the semiconductorsubstrate, may be replaced with an underlying layer 32, such as aninsulating layer or layers. For example, the same insulating layer orlayers used to form the gate dielectric underneath the active circuitfeatures, if they are part of the gate electrode, may be used. In oneembodiment, a triple gate oxide is formed underneath the second dummyfeature 28, as shown in FIG. 7. In one embodiment, the triple gate oxide32 is formed with nitrided oxide and has a thickness of approximately 20to 100 Angstroms. If the same material is used for the underlying layer32 and the gate dielectric, then the underlying layer 32 can be formedand patterned using conventional processing at the same time the gatedielectric is formed. Subsequently, the active circuit and dummyfeatures are formed. The presence of the underlying layer 32 helpsreduce substrate leakage by insulating the semiconductor substrate,which is under the underlying layer 32, from the expanded second dummyfeature 30.

FIGS. 1-7 illustrate how at least one dummy feature can be formed in thelayout 10 and how the layout 10 can be modified. Other parts of asemiconductor device or other semiconductor devices will have differentlayouts, which may result in the dummy features being formed inlocations different than that shown in FIGS. 5-7. FIG. 8 illustratesanother layout 40 that illustrates different locations for a dummyfeature that may arise in a semiconductor device layout. The layout 40in FIG. 8 is similar to the layout 10 in FIG. 1 in that the layout is ofthe same layer. The layout 40 includes a third active device region 42and fourth, fifth, and sixth active circuit features 44, 48, and 50 andregion 43, which is similar to region 25 in FIG. 1. (The same materialsand processes can be used to form the active device region and activecircuit features as those discussed for the equivalent features in FIG.1.) The portion 46 of the fourth active circuit feature 44 does not haveanother active circuit feature or a dummy feature nearby. Thus, placinga dummy feature near the portion 46 may be desirable. Using the methodsdescribed above, a dummy feature may be placed. In on embodiment, thedummy feature may be placed in contact with the sixth active circuitfeature 50. Thus, the third dummy feature 52 may be added to the layout40 using the same method used for forming the first and second dummyfeatures 26 and 28, but with the first distance being set so that itcoincides with the end of the sixth active feature 50.

In one embodiment, instead of spacing a dummy feature from the end of anactive circuit feature, the dummy feature may be made continuous withthe active circuit feature. As shown in FIG. 9, a third dummy feature 52is placed in the layout 40 so that it is continuous with the sixthactive circuit feature 50. The third dummy feature 52 may or may not bethe same width as the sixth active circuit feature 50. If the thirddummy feature 52 is the same width as the sixth active circuit feature50 adding the third dummy feature 52 to the end of the sixth activecircuit feature 50 so that the two features are in contact is the sameas extending the sixth active circuit feature 50 so it extends past theoriginal end of the active circuit feature 50. In other words, the thirddummy feature 52 can be viewed as an extension of the sixth activecircuit feature 50.

FIG. 10 illustrates that in one embodiment, instead of forming the thirddummy feature 52 at the end of the sixth active circuit feature 50, thethird dummy feature 52 can be formed over active circuit region 42.Therefore, any dummy feature can be formed over active circuit regionsareas or any other area of the layout.

The layouts described above are subsequently used to form layers of asemiconductor device using conventional methods, such asphotolithography and etch. Because one skilled in the art knows how toform a semiconductor device using a layout and understands how differentlayers are used to form a semiconductor device, details of suchprocessing will not be explained in any greater extent than thatconsidered necessary as illustrated above, for the understanding andappreciation of the underlying concepts of the present invention and inorder not to obfuscate or distract from the teachings of the presentinvention.

By now it should be appreciated that there has been provided placementand optimization of dummy features using a fast, robust, and efficientmethod. Altered model-based proximity correction methods are used toplace and optimize dummy features, in one embodiment. The dummy featuresare optimized for subsequent OPC processes, to reduce their electricalimpact, such as substrate leakage, capacitance or latchup. In addition,dummy features are placed near isolated or semi-isolated line-ends toreduce line-end pullback that occurs during etch and can not beprevented by only placing dummy features along the sides of activecircuit features.

In one embodiment, a method for forming a semiconductor structureincludes providing a semiconductor substrate, identifying an area thatcomprises an active device region, wherein the area has a perimeter at afirst location and at least a portion of the edge of the active deviceregion is coincident with at least a portion of the perimeter, expandingthe perimeter to a first distance away from the first location, whereinthe first distance defines a first point of a dummy feature, determininga second point of the dummy feature, adding the dummy feature to alayout using the first point and the second point, and using the layoutto form a layer in a semiconductor device. In one embodiment, thedistance between the first point and the second point defines a width ofthe dummy feature. In one embodiment, an edge of the dummy feature ismodified using an etch simulation result. In one embodiment, the area ischaracterized by a gate electrode and the perimeter of the areacomprises at least a portion of the edge of the gate electrode. In oneembodiment, determining a second point of the dummy feature furtherincludes expanding the perimeter to a second distance away from thefirst location, wherein; the second distance is greater than the firstdistance, subtracting the first distance from the second distance todetermine a width of the dummy feature, and placing the dummy feature sothat the edges of the dummy feature are along the first distance and thesecond distance. In one embodiment, adding the dummy feature ischaracterized by the placing the dummy feature. In one embodiment, theperimeter is continuous and in another embodiment, the perimeter isbroken. In one embodiment, an insulating layer is formed under the dummyfeature. In one embodiment, an area adjacent the dummy feature is doped,but the dummy feature is not doped.

In another embodiment, a method for forming a semiconductor devicehaving a dummy feature includes identifying a plurality of activecircuit features, wherein the plurality of active circuit features as agroup has a perimeter at a first location, expanding the perimeter to afirst distance away from the first location, expanding the perimeter toa second distance away from the first location, wherein the seconddistance is greater than the first distance, subtracting the firstdistance from the second distance to determine a width of the dummyfeature, and placing the dummy feature so that the edges of the dummyfeature are along the first distance and the second distance. In oneembodiment, the distance between the first point and the second pointdefine a width of the dummy feature.

In the foregoing specification, the invention has been described withreference to specific embodiments. However, one of ordinary skill in theart appreciates that various modifications and changes can be madewithout departing from the scope of the present invention as set forthin the claims below. For example, although only one layer was describedherein, a skilled artisan understands that this can be used for anylayer, such as a metal layer. Accordingly, the specification and figuresare to be regarded in an illustrative rather than a restrictive sense,and all such modifications are intended to be included within the scopeof the present invention.

Benefits, other advantages, and solutions to problems have beendescribed above with regard to specific embodiments. However, thebenefits, advantages, solutions to problems, and any element(s) that maycause any benefit, advantage, or solution to occur or become morepronounced are not to be construed as a critical, required, or essentialfeature or element of any or all the claims. As used herein, the terms“comprises,” “comprising,” or any other variation thereof, are intendedto cover a non-exclusive inclusion, such that a process, method,article, or apparatus that comprises a list of elements does not includeonly those elements but may include other elements not expressly listedor inherent to such process, method, article, or apparatus. The terms“a” or “an”, as used herein, are defined as one or more than one. Theterm “plurality”, as used herein, is defined as two or more than two.The term another, as used herein, is defined as at least a second ormore.

1. A method for forming a semiconductor structure, the methodcomprising: identifying an area that comprises an active device region,wherein the area has a perimeter at a first location and at least aportion of the edge of the active device region is coincident with atleast a portion of the perimeter; expanding the perimeter to a firstdistance away from the first location, wherein the first distancedefines a first point of a dummy feature; determining a second point ofthe dummy feature; adding the dummy feature to a layout using the firstpoint and the second point; and using the layout to form a layer in asemiconductor device.
 2. The method of claim 1, wherein the distancebetween the first point and the second point defines a width of thedummy feature.
 3. The method of claims 1, wherein an edge of the dummyfeature is modified using an etch simulation result.
 4. The method ofclaim 1, wherein the area is characterized by a gate electrode and theperimeter of the area comprises at least a portion of the edge of thegate electrode.
 5. The method of claim 1, wherein determining a secondpoint of the dummy feature further comprises: expanding the perimeter toa second distance away from the first location, wherein; the seconddistance is greater than the first distance; subtracting the firstdistance from the second distance to determine a width of the dummyfeature; and placing the dummy feature so that the edges of the dummyfeature are along the first distance and the second distance.
 6. Themethod of claim 5, wherein adding the dummy feature is characterized bythe placing the dummy feature.
 7. The method of claim 1, wherein theperimeter is continuous.
 8. The method of claim 1, wherein the perimeteris broken.
 9. The method of claim 1, wherein forming an insulating layerunder the dummy feature.
 10. The method of claim 1, wherein doping anarea adjacent the dummy feature and not doping the dummy feature. 11.The method of claim 2, wherein determining a second point of the dummyfeature further comprises: expanding the perimeter to a second distanceaway from the first location, wherein; the second distance is greaterthan the first distance; subtracting the first distance from the seconddistance to determine a width of the dummy feature; and placing thedummy feature so that the edges of the dummy feature are along the firstdistance and the second distance.
 12. The method of claims 2, wherein anedge of the dummy feature is modified using an etch simulation result.13. The method of claim 2, wherein the area is characterized by a gateelectrode and the perimeter of the area comprises at least a portion ofthe edge of the gate electrode.
 14. The method of claim 2, wherein theperimeter is continuous.
 15. The method of claim 2, wherein theperimeter is broken.
 16. The method of claim 2, wherein doping an areaadjacent the dummy feature and not doping the dummy feature.
 17. Themethod of claim 4, wherein forming an insulating layer under the dummyfeature.
 18. The method of claim 4, wherein doping an area adjacent thedummy feature and not doping the dummy feature.
 19. The method of claim4, wherein determining a second point of the dummy feature furthercomprises: expanding the perimeter to a second distance away from thefirst location, wherein; the second distance is greater than the firstdistance; subtracting the first distance from the second distance todetermine a width of the dummy feature; and placing the dummy feature sothat the edges of the dummy feature are along the first distance and thesecond distance.
 20. The method of claim 9, wherein determining a secondpoint of the dummy feature further comprises: expanding the perimeter toa second distance away from the first location, wherein; the seconddistance is greater than the first distance; subtracting the firstdistance from the second distance to determine a width of the dummyfeature; and placing the dummy feature so that the edges of the dummyfeature are along the first distance and the second distance.